Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing

Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the range of systolic array’s application, making the choice of the best systolic architecture to a given problem a critical task. In this work we investigate the specification and verification of such architectures using rewriting-logic, which provides a high level design framework for architectural exploration. In particular, we show how to use ELAN rewriting system to specify reconfigurable systems which can perform both arithmetic and symbolic computations.

• Type: Conference
• Year: 2003
• Where: FDL
• Authors: Mauricio Ayala-Rincón, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein
• Keywords: FDL 2003, Reconfigurable Systolic Arrays, Systolic Array, Systolic Array Application