Using Time Skewing to Eliminate Idle Time due to Memory Bandwidth and Network Limitations

Time skewing is a compile-time optimization that can provide arbitrarily high cache hit rates for a class of iterative calculations, given a sufficient number of time steps and sufficient cache memory. Thus, it can eliminate processor idle time caused by inadequate main memory bandwidth. In this article, we give a generalization of time skewing for multiprocessor architectures, and discuss time skewing for multilevel caches. Our generalization for multiprocessors lets us eliminate processor idle time caused by any combination of inadequate main memory bandwidth, limited network bandwidth, and high network latency, given a sufficiently large problem and sufficient cache. As in the uniprocessor case, the cache requirement grows with the machine balance rather than the problem size. Our techniques for using multilevel caches reduce the L1 cache requirement, which would otherwise be unacceptably high for some architectures when using arrays of high dimension.

• Type: Conference
• Year: 2000
• Where: IPPS
• Authors: David Wonnacott
• Keywords: Distributed And Parallel Computing, Inadequate Main Memory, IPPS 2000, Main Memory Bandwidth, Processor Idle Time