Variability-driven module selection with joint design time optimization and post-silicon tuning

Abstract-- Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection techniques in high level synthesis use worst case delay/power information to perform the optimization, and therefore may be too pessimistic such that extra resources are used to guarantee design requirements. Parametric yield, which is defined as the probability of the synthesized hardware meeting the performance/power constraints, can be used to guide design space exploration. The parametric yield can be effectively improved by combining both design-time variation-aware optimization and post silicon tuning techniques (such as adaptive body biasing (ABB)). In this paper, we propose a module selection algorithm that combines design-time optimization with postsilicon tuning (using ABB) to maximize design yield. A variation-aware module selection algorithm based on efficient performance and power yield gradient c...

• Type: Conference
• Year: 2008
• Where: ASPDAC
• Authors: Feng Wang 0004, Xiaoxia Wu, Yuan Xie
• Keywords: ASPDAC 2008, Hardware, Module Selection, Module Selection Algorithm, Module Selection Technique