Verification and Analysis of Self-Checking Properties through ATPG

Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to detect and compensate errors online. However, during synthesis and optimization self-checking properties can be destroyed. This paper shows how automatic test pattern generation (ATPG) can be used to analyze self-checking properties. As a result the properties are either verified or the fault detection profile provided by ATPG can be used to increase the error detection or fault tolerance capabilities of the design. Experimental data are shown for several self-checking arithmetic circuits.

• Type: Conference
• Year: 2008
• Where: IOLTS
• Authors: Marc Hunger, Sybille Hellebrand
• Keywords: IOLTS 2008, Optimization Self-checking Properties, Self-checking Circuits, Self-checking Properties, Software Engineering