A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance

A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than the Fastcap, which is a very advanced multipole-accelerated parasitic capacitance extractor now.

• Type: Conference
• Year: 2001
• Where: ASPDAC
• Authors: Zhaozhi Yang, Zeyi Wang, Shuzhou Fang
• Keywords: ASPDAC 2001, Charge Distribution, Computational Complexity, Hardware, Virtual 3-D Extractor