VLIW: a case study of parallelism verification

Parallelism in processor architecture and design imposes a verification challenge as the exponential growth in the number of execution combinations becomes unwieldy. In this paper we report on the verification of a Very Large Instruction Word processor. The verification team used a sophisticated test program generator that modeled the parallel aspects as sequential constraints, and augmented the tool with manually written test templates. The system created large numbers of legal stimuli, however the quality of the tests was proved insufficient by several post silicon bugs. We analyze this experience and suggest an alternative, parallel generation technique. We show through experiments the feasibility of the new technique and its superior quality along several dimensions. We claim that the results apply to other parallel architectures and verification environments. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids – Verification General Terms Design, Verification K...

• Type: Conference
• Year: 2005
• Where: DAC
• Authors: Allon Adir, Yaron Arbetman, Bella Dubrov, Yossi Lichtenstein, Michal Rimon, Michael Vinov, Massimo A. Calligaro, Andrew Cofler, Gabriel Duffy
• Keywords: Computer Architecture, DAC 2005, Keywords Functional Verification, Verification Challenge, Verification General Terms