A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms

The usefulness of an artificial analog neural network is closely bound to its trainability. This paper introduces a new analog neural network architecture using weights determined by a genetic algorithm. The first VLSI implementation presented in this paper achieves 200 giga connections per second with 4096 synapses on less than 1 mm2 silicon area. Since the training can be done at the full speed of the network, several hundred individuals per second can be tested by the genetic algorithm. This makes it feasible to tackle problems that require large multi-layered networks.

• Type: Conference
• Year: 2001
• Where: ICES
• Authors: Johannes Schemmel, Karlheinz Meier, Felix Schürmann
• Keywords: Analog Neural Network, Genetic Algorithm, Hardware, ICES 2001, Neural Network Architecture