A wave-pipelined router architecture using ternary associative memory

In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time and power. The design approach considered in this paper allows the propagation of data from stage to stage to occur without the use of intermediate latches. Control signals are used to ensure that intermixing of data waves does not occur. The results of the study show that wave-pipelining helps to reduce the clock period.

• Type: Conference
• Year: 2000
• Where: GLVLSI
• Authors: José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan
• Keywords: Clock Cycle Time, GLVLSI 2000, Router Architecture, VLSI, Wave-pipelining Scheme