Way Stealing:cache-assisted automatic instruction set extensions

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the register file alone and does not require expensive coherence protocols, as it does not add memory elements to the processor. When enhanced with Way Stealing, ISE identification flows detect more opportunities for acceleration than prior methods; consequently, Way Stealing can accelerate applications to up to 3.7?, whilst reducing the memory sub-system energy consumption by up to 67%, despite data-cache related restrictions. Categories and Subject Descriptors B.3.2 [Memory Structures]: Design Styles; D.3.4 [Programming Languages]: Processors--Optimization General Terms Design, Performance Keywords Application-Specific Processors, Instruction Set Extensions, Way Stealing, Memory Coherence, Automatic Identification

• Type: Conference
• Year: 2009
• Where: DAC
• Authors: Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon
• Keywords: DAC 2009, Design Automation, Instruction Set Extensions, Memory Sub-system Energy, Paper Introduces Way