WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches

Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able to accurately obtain the worstcase execution time (WCET) of applications running on multi-core platforms, which is very challenging due to the possible runtime inter-core interferences in using shared resources such as the shared L2 caches. As the first step toward time-predictable multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worstcase shared L2 instruction cache misses by considering inter-thr...

• Type: Conference
• Year: 2008
• Where: RTAS
• Authors: Jun Yan, Wei Zhang
• Keywords: Multi-core, Multi-core Computing, Real-Time Technology, RTAS 2008, Shared L2 Instruction