A wideband hierarchical circuit reduction for massively coupled interconnects

— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vector potential equivalent circuit) model, which not only enables the passive sparsification but also gives correct low-frequency response, whereas the recent  ¢¡¤£ circuit reduction intrinsically has inaccurate ¥§¦ value and low-frequency response due to nodal-susceptance formulation. Applying hierarchical circuit-reduction enhanced by multi-point expansions, we can obtain an accurate high-order impedance function to capture the high-frequency response. The impedance function is further enforced passivity by convex programming, and realized by a Foster’s synthesis. Experiments show that our method is as accurate as PRIMA in high frequency range, but leads to a realized circuit model with up to 10X times less complexity and up to 8X smaller simulation time. In addition, under the same reduction ratio...

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
• Keywords: ASPDAC 2005, Circuit Reduction, Hardware, Low-frequency Response, Realizable Circuit Reduction