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» A Caching Strategy to Improve iSCSI Performance
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IEEEPACT
2006
IEEE
14 years 1 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
PDP
2010
IEEE
13 years 12 months ago
hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
François Broquedis, Jérôme Cle...
SIGMETRICS
2012
ACM
251views Hardware» more  SIGMETRICS 2012»
11 years 10 months ago
Providing fairness on shared-memory multiprocessors via process scheduling
Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbate...
Di Xu, Chenggang Wu, Pen-Chung Yew, Jianjun Li, Zh...
ICCS
2009
Springer
14 years 2 months ago
Evaluation of Hierarchical Mesh Reorderings
Irregular and sparse scientific computing programs frequently experience performance losses due to inefficient use of the memory system in most machines. Previous work has shown t...
Michelle Mills Strout, Nissa Osheim, Dave Rostron,...
ICIAP
2009
ACM
14 years 8 months ago
Connected Component Labeling Techniques on Modern Architectures
In this paper we present an overview of the historical evolution of connected component labeling algorithms, and in particular the ones applied on images stored in raster scan orde...
Costantino Grana, Daniele Borghesani, Rita Cucchia...