This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Abstract. In this work, we develop novel file system, FRASH, for byteaddressable NVRAM (FRAM[1]) and NAND Flash device. Byte addressable NVRAM and NAND Flash is typified by the DRA...
Eun-ki Kim, Hyungjong Shin, Byung-gil Jeon, Seokhe...
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
We introduce and study problems of distributed observation with bounded or unbounded memory. We are given a system modeled as a finite-word language L over some finite alphabet ...
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...