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ICPADS
2007
IEEE
14 years 2 months ago
Scheduling multiple divisible loads on a linear processor network
Min, Veeravalli, and Barlas have recently proposed strategies to minimize the overall execution time of one or several divisible loads on a heterogeneous linear network, using one...
Matthieu Gallet, Yves Robert, Frédér...
IPPS
1999
IEEE
14 years 22 days ago
Run-Time Selection of Block Size in Pipelined Parallel Programs
Parallelizing compiler technology has improved in recent years. One area in which compilers have made progress is in handling DOACROSS loops, where crossprocessor data dependencie...
David K. Lowenthal, Michael James
PPOPP
2009
ACM
14 years 9 months ago
Mapping parallelism to multi-cores: a machine learning based approach
The efficient mapping of program parallelism to multi-core processors is highly dependent on the underlying architecture. This paper proposes a portable and automatic compiler-bas...
Zheng Wang, Michael F. P. O'Boyle
MCMASTER
1993
14 years 16 days ago
A Systolizing Compilation Scheme for Nested Loops with Linear Bounds
With the recent advances in massively parallel programmable processor networks, methods for the infusion of massive MIMD parallelism into programs have become increasingly relevant...
Michael Barnett, Christian Lengauer
RECONFIG
2008
IEEE
122views VLSI» more  RECONFIG 2008»
14 years 2 months ago
Using a CSP Based Programming Model for Reconfigurable Processor Arrays
The growing trend towards adoption of flexible and heterogeneous, parallel computing architectures has increased the challenges faced by the programming community. We propose a me...
Zain-ul-Abdin, Bertil Svensson