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DSN
2005
IEEE
14 years 2 months ago
Checking Array Bound Violation Using Segmentation Hardware
The ability to check memory references against their associated array/buffer bounds helps programmers to detect programming errors involving address overruns early on and thus avo...
Lap-Chung Lam, Tzi-cker Chiueh
JUCS
2010
130views more  JUCS 2010»
13 years 3 months ago
Toward an Integrated Tool Environment for Static Analysis of UML Class and Sequence Models
: There is a need for more rigorous analysis techniques that developers can use for verifying the critical properties in UML models. The UML-based Specification Environment (USE) t...
Wuliang Sun, Eunjee Song, Paul C. Grabow, Devon M....
SIGARCH
2008
97views more  SIGARCH 2008»
13 years 8 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
FAC
2007
128views more  FAC 2007»
13 years 8 months ago
Verifying a signature architecture: a comparative case study
Abstract. We report on a case study in applying different formal methods to model and verify an architecture for administrating digital signatures. The architecture comprises seve...
David A. Basin, Hironobu Kuruma, Kunihiko Miyazaki...
IWSSD
2000
IEEE
14 years 28 days ago
Issues in Analyzing the Behavior of Event Dispatching Systems
A good architecture is a necessary condition to guarantee that the expected levels of performance, availability, fault tolerance, and scalability are achieved by the implemented s...
Giovanni Bricconi, Emma Tracanella, Elisabetta Di ...