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ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
14 years 25 days ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman
IEICET
2006
114views more  IEICET 2006»
13 years 8 months ago
Synchronization Verification in System-Level Design with ILP Solvers
Concurrency is one of the most important issues in system-level design. Interleaving among parallel processes can cause an extremely large number of different behaviors, making de...
Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro ...
JACM
2006
98views more  JACM 2006»
13 years 8 months ago
Distribution sort with randomized cycling
Parallel independent disks can enhance the performance of external memory (EM) algorithms, but the programming task is often di cult. In this paper we develop randomized variants ...
Jeffrey Scott Vitter, David A. Hutchinson
STTT
2010
97views more  STTT 2010»
13 years 7 months ago
Distributed dynamic partial order reduction
Abstract. Runtime (dynamic) model checking is a promising verification methodology for real-world threaded software because of its many features, the prominent ones being: (i) it ...
Yu Yang, Xiaofang Chen, Ganesh Gopalakrishnan, Rob...
ICDAR
2009
IEEE
13 years 6 months ago
Unconstrained Handwritten Document Layout Extraction Using 2D Conditional Random Fields
The paper describes a new approach using a Conditional Random Fields (CRFs) to extract physical and logical layouts in unconstrained handwritten letters such as those sent by indi...
Florent Montreuil, Emmanuele Grosicki, Laurent Heu...