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» A Component Architecture for FPGA-Based, DSP System Design
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CLUSTER
2008
IEEE
14 years 3 months ago
Intelligent compilers
—The industry is now in agreement that the future of architecture design lies in multiple cores. As a consequence, all computer systems today, from embedded devices to petascale ...
John Cavazos
VEE
2009
ACM
613views Virtualization» more  VEE 2009»
14 years 3 months ago
BitVisor: a thin hypervisor for enforcing i/o device security
Virtual machine monitors (VMMs), including hypervisors, are a popular platform for implementing various security functionalities. However, traditional VMMs require numerous compon...
Takahiro Shinagawa, Hideki Eiraku, Kouichi Tanimot...
MAM
2007
113views more  MAM 2007»
13 years 8 months ago
A reconfigurable computing framework for multi-scale cellular image processing
Cellular computing architectures represent an important class of computation that are characterized by simple processing elements, local interconnect and massive parallelism. Thes...
Reid B. Porter, Jan R. Frigo, Al Conti, Neal R. Ha...
ISPASS
2003
IEEE
14 years 2 months ago
Performance study of a cluster runtime system for dynamic interactive stream-oriented applications
Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism, and high computational requirements, making ...
Arnab Paul, Nissim Harel, Sameer Adhikari, Bikash ...
TCAD
2008
102views more  TCAD 2008»
13 years 8 months ago
Fault-Tolerant Distributed Deployment of Embedded Control Software
Safety-critical feedback-control applications may suffer faults in the controlled plant as well as in the execution platform, i.e., the controller. Control theorists design the con...
Claudio Pinello, Luca P. Carloni, Alberto L. Sangi...