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DAC
2000
ACM
14 years 17 days ago
System design of active basestations based on dynamically reconfigurable hardware
– This paper describes the system design and implementation of Active Basestations, a novel application of the run-time reconfigurable hardware technology whose applications have...
Athanassios Boulis, Mani B. Srivastava
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
SICHERHEIT
2008
13 years 9 months ago
Efficiency Improvement for NTRU
Abstract: The NTRU encryption scheme is an interesting alternative to well-established encryption schemes such as RSA, ElGamal, and ECIES. The security of NTRU relies on the hardne...
Johannes Buchmann, Martin Döring, Richard Lin...
IPPS
2000
IEEE
14 years 17 days ago
Dynamic Data Layouts for Cache-Conscious Factorization of DFT
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Vi...
WMPI
2004
ACM
14 years 1 months ago
A low cost, multithreaded processing-in-memory system
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. ...