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» A Decompression Architecture for Low Power Embedded Systems
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ICMCS
2006
IEEE
154views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Design of Audio and Video decoder for the T-DMB Receiver
We present a low-power architectural MPEG-4 part-10 AVC/H.264 video and MPEG-4 BSAC audio decoder chip capable of delivering high-quality and high-compression in wireless multimed...
Bontae Koo, Juhyun Lee, Sekho Lee, Jinkyu Kim, Min...
ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Reliability-aware design for nanometer-scale devices
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
David Atienza, Giovanni De Micheli, Luca Benini, J...
FPL
2008
Springer
119views Hardware» more  FPL 2008»
13 years 9 months ago
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
Jan de Cuveland, Felix Rettig, Venelin Angelov, Vo...
CVIU
2010
115views more  CVIU 2010»
13 years 7 months ago
A modified model for the Lobula Giant Movement Detector and its FPGA implementation
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
Hongying Meng, Kofi Appiah, Shigang Yue, Andrew Hu...
OSDI
1994
ACM
13 years 9 months ago
Storage Alternatives for Mobile Computers
Mobile computers such as notebooks, subnotebooks, and palmtops require low weight, low power consumption, and good interactive performance. These requirements impose many challeng...
Fred Douglis, Ramón Cáceres, M. Fran...