714 search results - page 13 / 143 » A Decompression Architecture for Low Power Embedded Systems |
151
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IWSOC
2005
IEEE
15 years 10 months ago
2005
IEEE
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
133
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SAC
2005
ACM
15 years 10 months ago
2005
ACM
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
164
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WMPI
2004
ACM
15 years 10 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
DAC
2000
ACM
15 years 9 months ago
2000
ACM
119
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DAC
1997
ACM
15 years 8 months ago
1997
ACM
This paper presents a power evaluation framework designed for estimating power consumption of a new video telephone compression standard, ITU-H.263, at the system level. A hierarc...