A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
We present a tool which is designed to be used as a code compression advisory system for object code to be run on an embedded processor. All the compression schemes support run-ti...
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
This paper presents a power evaluation framework designed for estimating power consumption of a new video telephone compression standard, ITU-H.263, at the system level. A hierarc...