814 search results - page 24 / 163 » A Design of the Signal Processing Hardware Platform for Comm... |
ICASSP
2011
IEEE
13 years 29 days ago
2011
IEEE
Real-time streaming signal processing systems typically desire high throughput and low latency. Many such systems can be modeled as synchronous data flow graphs. In this paper, w...
IEEEPACT
2008
IEEE
14 years 3 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
HICSS
2002
IEEE
14 years 2 months ago
2002
IEEE
The location and configuration of transmission infrastructure for cellular communication networks is a complex engineering task involving many competing objectives. While minimis...
IPPS
1997
IEEE
14 years 1 months ago
1997
IEEE
This paper describes the design and implementation of the virtual memory-mapped communicationmodel (VMMC) on a Myrinet network of PCI-based PCs. VMMC has been designed and impleme...
ERSA
2009
13 years 7 months ago
2009
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...