162 search results - page 24 / 33 » A Distributed Cache Coherence Protocol for Hypercube Multipr... |
ICS
1993
Tsinghua U.
14 years 15 days ago
1993
Tsinghua U.
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
SC
1995
ACM
13 years 12 months ago
1995
ACM
The goal of this work is to explore architectural mechanisms for supporting explicit communication in cachecoherent shared memory multiprocessors. The motivation stems from the ob...
IPPS
2000
IEEE
14 years 24 days ago
2000
IEEE
The Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus) is a low-latency, high-bandwidth interconnection network which directly links arbitrary pairs of processor nodes wit...
CAL
2010
13 years 5 months ago
2010
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Much research has been devoted to making microprocessors energy-efficient. However, little attention has been paid to multiprocessor environments where, due to the co-operative na...