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» A Distributed Control Path Architecture for VLIW Processors
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IPPS
2007
IEEE
14 years 1 months ago
A Prototype Multithreaded Associative SIMD Processor
The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially...
Kevin Schaffer, Robert A. Walker
IFIP
1993
Springer
13 years 11 months ago
Self-Timed Architecture of a Reduced Instruction Set Computer
An advanced Self-Timed Reduced Instruction Set Computer (ST-RISC) architecture is described. It is designed hierarchically, and is formally specified functionally at the various ...
Ilana David, Ran Ginosar, Michael Yoeli
ISCC
2002
IEEE
144views Communications» more  ISCC 2002»
14 years 17 days ago
A hierarchical distributed protocol for MPLS path creation
Network service provisioning involves the control of network resources through signaling, routing and management protocols that achieve Quality of Service and Traffic Engineering ...
Mohamed El-Darieby, Dorina C. Petriu, Jerry Rolia
CASES
2009
ACM
14 years 2 months ago
CheckerCore: enhancing an FPGA soft core to capture worst-case execution times
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Ta...
ASAP
2005
IEEE
96views Hardware» more  ASAP 2005»
14 years 1 months ago
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
On public communication networks such as the Internet, data confidentiality can be provided by symmetric-key ciphers. One of the most common operations used in symmetric-key ciphe...
A. Murat Fiskiran, Ruby B. Lee