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» A Distributed Control Path Architecture for VLIW Processors
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IPPS
2005
IEEE
14 years 1 months ago
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application
In this paper, we propose an IPSec implementation on Xilinx Virtex-II Pro FPGA1 . We move the key management and negotiation into software function calls that run on the PowerPC p...
Jing Lu, John W. Lockwood
DSN
2004
IEEE
13 years 11 months ago
Impact of Path Diversity on Multi-homed and Overlay Networks
Multi-homed and overlay networks are two widely studied approaches aimed at leveraging the inherent redundancy of the Internet's underlying routing infrastructure to enhance ...
Junghee Han, Farnam Jahanian
ENTCS
2002
89views more  ENTCS 2002»
13 years 7 months ago
ZEUS: A Distributed Timed Model-Checker Based on KRONOS
In this work we present Zeus, a Distributed Model-Checker that evolves from the tool Kronos [8] and that currently can handle backwards computation of TCTLreachability properties ...
Víctor A. Braberman, Alfredo Olivero, Ferna...
HPCA
2002
IEEE
14 years 8 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...
CONPAR
1994
13 years 11 months ago
The Rewrite Rule Machine Node Architecture and Its Performance
The Rewrite Rule Machine (RRM) is a massively parallel MIMD/SIMD computer designed with the explicit purpose of supporting veryhigh-level parallel programming with rewrite rules. T...
Patrick Lincoln, José Meseguer, Livio Ricci...