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HPCA
1996
IEEE
13 years 11 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
HPCA
2009
IEEE
14 years 8 months ago
Prediction router: Yet another low latency on-chip router architecture
Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...
SAC
2006
ACM
13 years 7 months ago
Combining supervised and unsupervised monitoring for fault detection in distributed computing systems
Fast and accurate fault detection is becoming an essential component of management software for mission critical systems. A good fault detector makes possible to initiate repair a...
Haifeng Chen, Guofei Jiang, Cristian Ungureanu, Ke...
EDOC
2003
IEEE
14 years 25 days ago
Integrating CBSE, SoC, MDA, and AOP in a Software Development Method
Component-Based Software Engineering, Separation of Concerns, Model-Driven Architecture, and Aspect-Oriented Programming are four active research areas that have been around for s...
Raul Silaghi, Alfred Strohmeier
BC
2008
73views more  BC 2008»
13 years 7 months ago
Interaction of ON and OFF pathways for visual contrast measurement
We propose a novel model of visual contrast measurement based on segregated ON and OFF pathways. Two driving forces have shaped our investigation: (1) establishing a mechanism sele...
Heiko Neumann, Luiz Pessoa, Thorsten Hansen