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» A Dynamically Adaptable Hardware Transactional Memory
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ISCA
2007
IEEE
177views Hardware» more  ISCA 2007»
14 years 1 months ago
Adaptive insertion policies for high performance caching
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, ...
CASES
2008
ACM
13 years 9 months ago
Efficient code caching to improve performance and energy consumption for java applications
Java applications rely on Just-In-Time (JIT) compilers or adaptive compilers to generate and optimize binary code at runtime to boost performance. In conventional Java Virtual Mac...
Yu Sun, Wei Zhang
MICRO
1997
IEEE
128views Hardware» more  MICRO 1997»
13 years 11 months ago
Run-Time Spatial Locality Detection and Optimization
As the disparity between processor and main memory performance grows, the number of execution cycles spent waiting for memory accesses to complete also increases. As a result, lat...
Teresa L. Johnson, Matthew C. Merten, Wen-mei W. H...
VEE
2005
ACM
218views Virtualization» more  VEE 2005»
14 years 1 months ago
The pauseless GC algorithm
Modern transactional response-time sensitive applications have run into practical limits on the size of garbage collected heaps. The heap can only grow until GC pauses exceed the ...
Cliff Click, Gil Tene, Michael Wolf
JCP
2008
190views more  JCP 2008»
13 years 7 months ago
Real-time System Identification of Unmanned Aerial Vehicles: A Multi-Network Approach
In this paper, real-time system identification of an unmanned aerial vehicle (UAV) based on multiple neural networks is presented. The UAV is a multi-input multi-output (MIMO) nonl...
Vishwas R. Puttige, Sreenatha G. Anavatti