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FCCM
1998
IEEE
148views VLSI» more  FCCM 1998»
13 years 11 months ago
JHDL - An HDL for Reconfigurable Systems
JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard pro...
Peter Bellows, Brad L. Hutchings
EUC
2006
Springer
13 years 11 months ago
A Processor Extension for Cycle-Accurate Real-Time Software
Certain hard real-time tasks demand precise timing of events, but the usual software solution of periodic interrupts driving a scheduler only provides precision in the millisecond ...
Nicholas Jun Hao Ip, Stephen A. Edwards
SAC
2010
ACM
13 years 9 months ago
Reactive parallel processing for synchronous dataflow
The control flow of common processors does not match the specific needs of reactive systems. Key issues for these systems are preemption and concurrency, combined with timing pred...
Claus Traulsen, Reinhard von Hanxleden
FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
13 years 9 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
ERSA
2008
145views Hardware» more  ERSA 2008»
13 years 9 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione