107 search results - page 3 / 22 » A Fine-Grain Parallel Architecture Based on Barrier Synchron... |
IEEEPACT
2000
IEEE
13 years 11 months ago
2000
IEEE
ÐThis paper presents a multithreaded abstract machine for the TyCO process calculus. We argue that process calculi provide a powerful framework to reason about fine-grained parall...
IEEEINTERACT
2003
IEEE
13 years 12 months ago
2003
IEEE
This paper introduces a method for improving program run-time performance by gathering work in an application and executing it efficiently in an integrated thread. Our methods ext...
IPPS
2010
IEEE
13 years 3 months ago
2010
IEEE
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
IPPS
1997
IEEE
13 years 10 months ago
1997
IEEE
Barrier synchronization is a crucial operation for parallel systems. Many schemes have been proposed in the literature to achieve fast barrier synchronization through software, ha...
ASAP
1996
IEEE
13 years 10 months ago
1996
IEEE
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...