36 search results - page 4 / 8 » A Flexible Hardware Encoder for Low-Density Parity-Check Cod... |
ISMVL
2005
IEEE
14 years 1 months ago
2005
IEEE
A novel duplex asynchronous data-transfer scheme based on multiple-valued encoding is proposed for interleaving in Low-Density Parity-Check (LDPC) decoders, where high-throughput ...
CORR
2006
Springer
13 years 7 months ago
2006
Springer
Abstract-- An elementary combinatorial Tanner graph construction for a family of near-regular low density parity check (LDPC) codes achieving high girth is presented. These codes a...
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— In this paper, we investigate the application of nonbinary low density parity check (LDPC) codes over Galois field GF(q) for both single-input single-output (SISO) and...
SIPS
2007
IEEE
14 years 1 months ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...