39 search results - page 6 / 8 » A Formal Verification Environment for Railway Signaling Syst... |
ASE
2008
13 years 8 months ago
2008
Model checkers were originally developed to support the formal verification of high-level design models of distributed system designs. Over the years, they have become unmatched in...
ICSE
2000
IEEE-ACM
13 years 11 months ago
2000
IEEE-ACM
This paper describes an experiment to use the Spin model checking system to support automated verification of time partitioning in the Honeywell DEOS real-time scheduling kernel. ...
DSN
2004
IEEE
13 years 11 months ago
2004
IEEE
It is often the case that safety-critical systems have to be reconfigured during operation because of issues such as changes in the system's operating environment or the fail...
TCAD
2008
13 years 7 months ago
2008
Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
CORR
2010
Springer
13 years 8 months ago
2010
Springer
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...