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WOTUG
2008
13 years 10 months ago
2008
Abstract. This paper considers the issues involved in translating specifications described in the CSP B formal method into Handel-C. There have previously been approaches to transl...
CODES
2009
IEEE
14 years 23 days ago
2009
IEEE
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a softwarelike ...
IWMM
2010
Springer
14 years 1 months ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
CGO
2003
IEEE
14 years 2 months ago
2003
IEEE
Many processor architectures provide a set of addressing modes in their address generation units. For example DSPs (digital signal processors) have powerful addressing modes for e...
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...