21 search results - page 1 / 5 » A Generic Dual Core Architecture with Error Containment |
CAI
2004
Springer
13 years 11 months ago
2004
Springer
The dual core strategy allows to construct a fail-silent processor from two instances (master/checker) of any arbitrary standard processor. Its main drawbacks are its vulnerability...
DSN
2006
IEEE
14 years 5 months ago
2006
IEEE
DFT
2006
IEEE
14 years 5 months ago
2006
IEEE
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic informa...
IESS
2007
Springer
14 years 5 months ago
2007
Springer
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
AHS
2006
IEEE
14 years 5 months ago
2006
IEEE
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...