Sciweavers

10 search results - page 2 / 2
» A Generic Network Interface Architecture for a Networked Pro...
Sort
View
136
Voted
CLUSTER
2009
IEEE
15 years 8 months ago
A scalable and generic task scheduling system for communication libraries
Abstract—Since the advent of multi-core processors, the physionomy of typical clusters has dramatically evolved. This new massively multi-core era is a major change in architectu...
François Trahay, Alexandre Denis
148
Voted
PDP
2009
IEEE
15 years 10 months ago
Phoenix: A Runtime Environment for High Performance Computing on Chip Multiprocessors
Abstract—Execution of applications on upcoming highperformance computing (HPC) systems introduces a variety of new challenges and amplifies many existing ones. These systems will...
Avneesh Pant, Hassan Jafri, Volodymyr V. Kindraten...
223
Voted

Lecture Notes
1005views
17 years 3 months ago
Lectures on reconfigurable computing
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
Sherief Reda
161
Voted
IJCNN
2000
IEEE
15 years 7 months ago
Pose Classification Using Support Vector Machines
The field of human-computer interaction has been widely investigated in the last years, resulting in a variety of systems used in different application fields like virtual reality...
Edoardo Ardizzone, Antonio Chella, Roberto Pirrone
147
Voted
NOCS
2007
IEEE
15 years 10 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...