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ASPDAC
2001
ACM
137views Hardware» more  ASPDAC 2001»
13 years 11 months ago
Optimized address assignment for DSPs with SIMD memory accesses
This paper deals with address assignment in code generation for digital signal processors (DSPs) with SIMD (single instruction multiple data) memory accesses. In these processors ...
Markus Lorenz, David Koffmann, Steven Bashford, Ra...
PDP
2003
IEEE
14 years 22 days ago
Scheduling strategies for mixed data and task parallelism on heterogeneous clusters and grids
We consider the execution of a complex application on a heterogeneous "grid" computing platform. The complex application consists of a suite of identical, independent pr...
Olivier Beaumont, Arnaud Legrand, Yves Robert
ICS
2007
Tsinghua U.
14 years 1 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
INFOCOM
2009
IEEE
14 years 2 months ago
MARA: Maximum Alternative Routing Algorithm
—In hop-by-hop networks, provision of multipath routes for all nodes can improve fault tolerance and performance. In this paper we study the multipath route calculation by constr...
Yasuhiro Ohara, Shinji Imahori, Rodney Van Meter
PC
2007
161views Management» more  PC 2007»
13 years 7 months ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...