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DATE
2003
IEEE
124views Hardware» more  DATE 2003»
14 years 2 months ago
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...
Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, Ting...
ISQED
2009
IEEE
124views Hardware» more  ISQED 2009»
14 years 4 months ago
Revisiting the linear programming framework for leakage power vs. performance optimization
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
Kwangok Jeong, Andrew B. Kahng, Hailong Yao
HPCA
1998
IEEE
14 years 1 months ago
Address Translation Mechanisms In Network Interfaces
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host. NIs that support user-level messaging avoid frequent ope...
Ioannis Schoinas, Mark D. Hill
PPL
2008
144views more  PPL 2008»
13 years 9 months ago
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (d2-CMP) Using FPGAs
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...
Konstantinos Tatas, Costas Kyriacou, Paraskevas Ev...
ILP
2004
Springer
14 years 2 months ago
Improving Rule Evaluation Using Multitask Learning
Abstract. This paper introduces Deft, a new multitask learning approach for rule learning algorithms. Like other multitask learning systems, the one proposed here is able to improv...
Mark D. Reid