1998 search results - page 112 / 400 » A Hardware Implementation of PRAM and Its Performance Evalua... |
161
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
: Over the years, many design methodologies/tools and layout architectures have been developed for datapath-oriented designs. One commonly used approach for high-speed datapath des...
165
Voted
ISQED
2009
IEEE
16 years 18 days ago
2009
IEEE
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
200
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HPCA
1998
IEEE
15 years 10 months ago
1998
IEEE
Good network hardware performance is often squandered by overheads for accessing the network interface (NI) within a host. NIs that support user-level messaging avoid frequent ope...
177
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PPL
2008
15 years 5 months ago
2008
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronizati...
167
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ILP
2004
Springer
15 years 11 months ago
2004
Springer
Abstract. This paper introduces Deft, a new multitask learning approach for rule learning algorithms. Like other multitask learning systems, the one proposed here is able to improv...