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» A Hardware Implementation of PRAM and Its Performance Evalua...
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PC
2007
284views Management» more  PC 2007»
13 years 8 months ago
Implementation and evaluation of shared-memory communication and synchronization operations in MPICH2 using the Nemesis communic
This paper presents the implementation of MPICH2 over the Nemesis communication subsystem and the evaluation of its shared-memory performance. We describe design issues as well as...
Darius Buntinas, Guillaume Mercier, William Gropp
EH
2002
IEEE
161views Hardware» more  EH 2002»
14 years 1 months ago
An Immunochip Architecture and Its Emulation
The paper proposes an architecture for building immunochips and provides a mathematical framework in describing some of its operations using the concepts of proteins and immune ne...
Alexander O. Tarakanov, Dipankar Dasgupta
ICS
2000
Tsinghua U.
14 years 17 days ago
Improving parallel system performance by changing the arrangement of the network links
The Midimew network is an excellent contender for implementing the communication subsystem of a high performance computer. This network is an optimal 2D topology in the sense ther...
Valentin Puente, Cruz Izu, José A. Gregorio...
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 5 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
MSS
2005
IEEE
175views Hardware» more  MSS 2005»
14 years 2 months ago
High Performance Storage System Scalability: Architecture, Implementation and Experience
The High Performance Storage System (HPSS) provides scalable hierarchical storage management (HSM), archive, and file system services. Its design, implementation and current domin...
Richard W. Watson