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SECON
2007
IEEE
14 years 3 months ago
A SoC-based Sensor Node: Evaluation of RETOS-enabled CC2430
—Recent progress in Wireless Sensor Networks technology has enabled many complicated real-world applications. Some of the applications demand a non-trivial amount of computation;...
Sukwon Choi, Hojung Cha, SungChil Cho
HPDC
2012
IEEE
11 years 11 months ago
VNET/P: bridging the cloud and high performance computing through fast overlay networking
networking with a layer 2 abstraction provides a powerful model for virtualized wide-area distributed computing resources, including for high performance computing (HPC) on collec...
Lei Xia, Zheng Cui, John R. Lange, Yuan Tang, Pete...
ASPDAC
2000
ACM
131views Hardware» more  ASPDAC 2000»
14 years 18 days ago
Reconfigurable synchronized dataflow processor
- This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow ...
Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka...
SPAA
2010
ACM
14 years 1 months ago
Implementing and evaluating nested parallel transactions in software transactional memory
Transactional Memory (TM) is a promising technique that simplifies parallel programming for shared-memory applications. To date, most TM systems have been designed to efficientl...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
14 years 2 months ago
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
Se-Hyun Yang, Babak Falsafi