1998 search results - page 265 / 400 » A Hardware Implementation of PRAM and Its Performance Evalua... |
169
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WMPI
2004
ACM
15 years 11 months ago
2004
ACM
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
169
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HPCA
2000
IEEE
15 years 10 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
173
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ACSAC
2005
IEEE
15 years 12 months ago
2005
IEEE
We present the sHype hypervisor security architecture and examine in detail its mandatory access control facilities. While existing hypervisor security approaches aiming at high a...
162
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DSN
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes the design, implementation, and performance evaluation of ST-TCP (Server fault-Tolerant TCP), which is an extension of TCP to tolerate TCP server failures. Th...
154
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IPPS
2000
IEEE
15 years 10 months ago
2000
IEEE
In order to reduce the overhead of synchronizing operations of shared memory multiprocessors, this paper proposes a mechanism, named specMEM, to execute memory accesses following ...