Sciweavers

1998 search results - page 269 / 400
» A Hardware Implementation of PRAM and Its Performance Evalua...
Sort
View
CLUSTER
2008
IEEE
16 years 19 days ago
Impact of topology and link aggregation on a PC cluster with Ethernet
Abstract—In addition to its use in local area networks, Ethernet has been used for connecting hosts in the area of highperformance computing. Here, we investigated the impact of ...
Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroya...
EUROSYS
2011
ACM
14 years 9 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang
SIGMETRICS
1996
ACM
174views Hardware» more  SIGMETRICS 1996»
15 years 10 months ago
Embra: Fast and Flexible Machine Simulation
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
Emmett Witchel, Mendel Rosenblum
SIGMETRICS
1992
ACM
128views Hardware» more  SIGMETRICS 1992»
15 years 10 months ago
MemSpy: Analyzing Memory System Bottlenecks in Programs
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...
Margaret Martonosi, Anoop Gupta, Thomas E. Anderso...
SIGOPS
2010
179views more  SIGOPS 2010»
15 years 27 days ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...