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» A Hardware Implementation of PRAM and Its Performance Evalua...
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MSS
2000
IEEE
160views Hardware» more  MSS 2000»
14 years 1 months ago
Implementation of a Fault-Tolerant Real-Time Network-Attached Storage Device
Phoenix is a fault-tolerantreal-time network-attachedstorage device (NASD). Like other NASD architectures, Phoenix provides an object-based interface to data stored on network-att...
Ashish Raniwala, Srikant Sharma, Anindya Neogi, Tz...
VLDB
1991
ACM
185views Database» more  VLDB 1991»
14 years 20 days ago
Experimental Evaluation of Real-Time Optimistic Concurrency Control Schemes
Due to its potential for a high degree of parallelism, optimistic concurrency control is expected to perform better than two-phase locking when integrated with priority-driven CPU...
Jiandong Huang, John A. Stankovic, Krithi Ramamrit...
IPPS
2000
IEEE
14 years 1 months ago
On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
Alberto Ferreira de Souza, Peter Rounce
APCSAC
2001
IEEE
14 years 24 days ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
EGH
2004
Springer
14 years 27 days ago
Understanding the efficiency of GPU algorithms for matrix-matrix multiplication
Utilizing graphics hardware for general purpose numerical computations has become a topic of considerable interest. The implementation of streaming algorithms, typified by highly ...
Kayvon Fatahalian, Jeremy Sugerman, Pat Hanrahan