Sciweavers

1998 search results - page 99 / 400
» A Hardware Implementation of PRAM and Its Performance Evalua...
Sort
View
EUROPAR
2001
Springer
14 years 1 months ago
VIA Communication Performance on a Gigabit Ethernet Cluster
As the technology for high-speed networks has evolved over the last decade, the interconnection of commodity computers (e.g., PCs and workstations) at gigabit rates has become a re...
Mark Baker, Paul A. Farrell, Hong Ong, Stephen L. ...
FPGA
2009
ACM
150views FPGA» more  FPGA 2009»
14 years 4 months ago
Bus mastering PCI express in an FPGA
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining...
Ray Bittner
IPPS
2003
IEEE
14 years 2 months ago
Reconfigurable Architecture Requirements for Co-Designed Virtual Machines
This paper addresses the physical hardware requirements necessary for a co-design hardware/software virtual machine to not only exist, but to also provide comparable performance w...
Kenneth B. Kent, Micaela Serra
IPPS
2006
IEEE
14 years 3 months ago
Towards building a highly-available cluster based model for high performance computing
In recent years, we have witnessed a growing interest in high performance computing (HPC) using a cluster of workstations. However, many challenges remain to be resolved before th...
Azzedine Boukerche, Raed Al-Shaikh, Mirela Sechi M...
TII
2008
88views more  TII 2008»
13 years 9 months ago
Performing Flexible Control on Low-Cost Microcontrollers Using a Minimal Real-Time Kernel
In recent years, approaches to control performance and resource optimization for embedded control systems have been receiving increased attention. Most of them focus on theory, whe...
Ricardo Marau, Pedro Leite, Manel Velasco, Pau Mar...