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» A High Performance Kernel-Less Operating System Architecture
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JSA
2010
158views more  JSA 2010»
13 years 3 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
VRST
2005
ACM
14 years 1 months ago
Human performance in space telerobotic manipulation
This paper considers the utility of VR in the design of the interface to a space-based telerobotic manipulator. An experiment was conducted to evaluate the potential for improved ...
Philip Lamb, Dean Owen
DEXAW
1997
IEEE
86views Database» more  DEXAW 1997»
14 years 13 days ago
Log-Only Temporal Object Storage
As main memory capacity increases, more of the database read requests will be satis ed from the bu er system. Consequently, the amount of disk write operations relative to disk re...
Kjetil Nørvåg, Kjell Bratbergsengen
ICC
2007
IEEE
119views Communications» more  ICC 2007»
14 years 2 months ago
Performance Measurement, Evaluation and Analysis of Push-to-Talk in 3G Networks
— Push-to-talk over Cellular (PoC) is considered as one of important applications in Next Generation Networks (NGN). The main objective of this study is to investigate the perfor...
Wei-Peng Chen, Steven Licking, Takashi Ohno, Satos...
TC
2010
13 years 6 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers