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» A Java processor architecture for embedded real-time systems
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VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
14 years 9 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
SBACPAD
2009
IEEE
155views Hardware» more  SBACPAD 2009»
14 years 3 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. ...
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C...
SAMOS
2005
Springer
14 years 2 months ago
Automatic ADL-Based Assembler Generation for ASIP Programming Support
Abstract. Systems-on-Chip (SoCs) may be built upon general purpose CPUs or application-specific instruction-set processors (ASIPs). On the one hand, ASIPs allow a tradeoff betwee...
Leonardo Taglietti, José O. Carlomagno Filh...
DAC
2012
ACM
11 years 11 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
CODES
2006
IEEE
14 years 2 months ago
Multi-processor system design with ESPAM
For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by emb...
Hristo Nikolov, Todor Stefanov, Ed F. Deprettere