The objective of this paper is to investigate the problems related to the extensional integration of information sources. In particular, we propose an approach for managing incons...
We propose a framework for the formal speci cation and veri cation of timed and hybrid systems. For timed systems we propose a speci cation language that refers to time only throug...
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
We present a static analysis that infers both upper and lower bounds on the usage that a logic program makes of a set of user-definable resources. The inferred bounds will in gener...
— The use of design patterns usually changes the approach of software design and makes software development relatively easy. This paper extends work on a forensic model for Logic...