1410 search results - page 142 / 282 » A Logic for Virtual Memory |
121
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ISCA
1993
IEEE
15 years 8 months ago
1993
IEEE
In this paper we introduce a classification of misses in shared-memory multiprocessors based on inter processor communication. We identify the set of essential misses, i.e., the s...
134
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IOLTS
2008
IEEE
15 years 11 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
136
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HIPEAC
2005
Springer
15 years 10 months ago
2005
Springer
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
139
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EUROCAST
2003
Springer
15 years 9 months ago
2003
Springer
This paper explores the computational capacity of a novel local computational model that expands the conventional analogical and logical dynamic neural models, based on the charge ...
140
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EUROMICRO
1998
IEEE
15 years 8 months ago
1998
IEEE
Several studies have demonstrated that out-of-order execution processors may not be the most adequate organization for wide issue processors due to the increasing penalties that w...