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ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
14 years 2 months ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...
PTS
2008
109views Hardware» more  PTS 2008»
13 years 10 months ago
Runtime Verification of C Programs
We present in this paper a framework, RMOR, for monitoring the execution of C programs against state machines, expressed in a textual (nongraphical) format in files separate from t...
Klaus Havelund
ECCV
2006
Springer
14 years 10 months ago
Multivalued Default Logic for Identity Maintenance in Visual Surveillance
Recognition of complex activities from surveillance video requires detection and temporal ordering of its constituent "atomic" events. It also requires the capacity to ro...
Vinay D. Shet, David Harwood, Larry S. Davis
AI
2004
Springer
13 years 8 months ago
Order-sorted logic programming with predicate hierarchy
Order-sorted logic has been formalized as first-order logic with sorted terms where sorts are ordered to build a hierarchy (called a sort-hierarchy). These sorted logics lead to u...
Ken Kaneiwa
CHI
2005
ACM
14 years 9 months ago
Flexible timeline user interface using constraints
Authoring tools routinely include a timeline representation to allow the author to specify the sequence of animations and interactions. However, traditional static timelines are b...
Kazutaka Kurihara, David Vronay, Takeo Igarashi