Sciweavers

1604 search results - page 227 / 321
» A Logical Viewpoint on Architectures
Sort
View
MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
14 years 5 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 4 months ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian
AI
2007
Springer
14 years 4 months ago
Constructing a User Preference Ontology for Anti-spam Mail Systems
The judgment that whether an email is spam or non-spam may vary from person to person. Different individuals can have totally different responses to the same email based on their p...
Jongwan Kim, Dejing Dou, Haishan Liu, Donghwi Kwak
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
14 years 4 months ago
GlitchLess: an active glitch minimization technique for FPGAs
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
14 years 4 months ago
Optimization of regular expression pattern matching circuits on FPGA
Regular expressions are widely used in Network Intrusion Detection System (NIDS) to represent patterns of network attacks. Since traditional software-only NIDS cannot catch up to ...
Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang,...