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» A Logical Viewpoint on Architectures
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ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
12 years 11 months ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
Christian Stoif, Martin Schoeberl, Benito Liccardi...
ISQED
2011
IEEE
309views Hardware» more  ISQED 2011»
12 years 11 months ago
Modeling and analyzing NBTI in the presence of Process Variation
With continuous scaling of transistors in each technology generation, NBTI and Process Variation (PV) have become very important silicon reliability problems for the microprocesso...
Taniya Siddiqua, Sudhanva Gurumurthi, Mircea R. St...
CN
2011
111views more  CN 2011»
12 years 11 months ago
On the design of network control and management plane
We provide a design of a control and management plane for data networks using the abstraction of 4D architecture, utilizing and extending 4D’s concept of a logically centralized...
Hammad Iqbal, Taieb Znati
ISPD
2012
ACM
252views Hardware» more  ISPD 2012»
12 years 3 months ago
Towards layout-friendly high-level synthesis
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabha...
DAC
2009
ACM
14 years 9 months ago
Online cache state dumping for processor debug
Post-silicon processor debugging is frequently carried out in a loop consisting of several iterations of the following two key steps: (i) processor execution for some duration, fo...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...