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PPSC
2001
14 years 16 days ago
A Mathematical Cache Miss Analysis for Pointer Data Structures
As the gap between processor and memory performance widens, careful analyses and optimizations of cache memory behavior become increasingly important. While analysis of regular lo...
Hongli Zhang, Margaret Martonosi
MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
14 years 4 months ago
Pointer cache assisted prefetching
Data prefetching effectively reduces the negative effects of long load latencies on the performance of modern processors. Hardware prefetchers employ hardware structures to predic...
Jamison D. Collins, Suleyman Sair, Brad Calder, De...
EUROPAR
2003
Springer
14 years 4 months ago
Compression in Data Caches with Compressible Field Isolation for Recursive Data Structures
We introduce a software/hardware scheme called the Field Array Compression Technique (FACT) which reduces cache misses due to recursive data structures. Using a data layout transfo...
Masamichi Takagi, Kei Hiraki
ACMMSP
2005
ACM
101views Hardware» more  ACMMSP 2005»
14 years 4 months ago
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and m...
Chris Lattner, Vikram S. Adve
VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
14 years 5 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl