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MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
13 years 11 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
13 years 11 months ago
Better Global Scheduling Using Path Profiles
Path profiles record the frequencies of execution paths through a program. Until now, the best global instruction schedulers have relied upon profile-gathered frequencies of condi...
Cliff Young, Michael D. Smith
ISCA
1999
IEEE
90views Hardware» more  ISCA 1999»
13 years 11 months ago
Selective Value Prediction
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
Brad Calder, Glenn Reinman, Dean M. Tullsen
ICPP
2009
IEEE
14 years 2 months ago
Code Semantic-Aware Runahead Threads
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
Tanausú Ramírez, Alex Pajuelo, Olive...
ITNG
2007
IEEE
14 years 1 months ago
Computational Power of the Quantum Turing Automata
Lots of efforts in the last decades have been done to prove or disprove whether the set of polynomially bounded problems is equal to the set of polynomially verifiable problems. T...
Sina Jafarpour, Mohammad Ghodsi, Keyvan Sadri, Zuh...